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Lecture

ASIC/FPGA design and verification techniques with tips and tricks and bug avoidance

About

The talk will give a prerequisite of ASIC and FPGA, and their interface technologies. Following some examples of design and test strategy with tips and tricks to ease the verification and validation process from past design experience. Also Included are some techniques on how to avoid and eliminate bugs.

Speaker: Dr Ching Man

Time/Date: Monday 8 April 7:15pm. refreshments 7pm

Design and Manufacturing
Electronics
Electronics Design
Information and Communications

1

Continuing Professional Development

This event can contribute towards your Continuing Professional Development (CPD) hours as part of the IET's CPD monitoring scheme.

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08 Apr 2024  

7:15pm - 8:15pm

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Organisers

  • Ireland Local Network

Registration information

TRiSS seminar room, TCD, Map

Poster

 

Location

TRiSS seminar room, 6th Floor Sutherland Centre, Arts Building, Trinity College, Dublin

TCD, Nassau st entrance
Dublin
Dublin
D02 CX56
IE

Enter the TCD Arts Centre via the Nassau St entrance. Travel via the lift to the 6th floor to enter the TRiSS venue , where the seminar room is located. 

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Registration

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Free of charge